1. Field of the Invention
The present invention relates to a two-dimensional solid-state image pickup device, and in particular to isolation of a CCD type solid-state image pickup device.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating the arrangement of a common interline CCD type solid-state image pickup device. The interline CCD type solid-state image pickup device comprises: a pickup unit 100, wherein are arranged a plurality of rows of photodiodes 101 and a plurality of vertical CCD registers 102, which receive and transfer electric charges from the photodiodes 101; a horizonal CCD register 300, for receiving electric charges from the vertical CCD registers 102 and transferring them via a vertical-horizonal transfer gate 200; an electric charge detector 400, for detecting the electric charges transferred by the horizontal CCD register 300; and an output amplifier 500. The portion enclosed by the broken lines is a unit pixel 103.
A solid-state image pickup device that is disclosed as the second embodiment in Japanese Unexamined Patent Publication No. Sho 63-150960 will now be described as the prior art. FIGS. 2A to 2D are diagrams illustrating a conventional unit pixel. FIG. 2A is a plan view; FIG. 2B is a cross sectional view taken along line IIB--IIB in FIG. 2A; FIG. 2C is a cross sectional view taken along line IIC--IIC in FIG. 2A; and FIG. 2D is a cross sectional view taking along line IID--IID in FIG. 2A. The structure of a pixel will be first described. A P well 2 is deposited on one main face of an N silicon substrate 1. A first N diffusion layer 3, constituting a photodiode 101, is formed in the surface of the P well 2, and a fourth P diffusion layer 4 having a high density is formed on the surface of the first N diffusion layer 3 to suppress the occurrence of a dark current. A second N diffusion layer 5, constituting the vertical CCD register 102, and a P diffusion layer 6 are formed in the named order. A first P diffusion layer 8-1 having a high density is present as an isolation layer on the side between the first and the second N diffusion layers 3 and 5 where a read gate 7 is not located, and a second P diffusion layer 8-2 is present on the other portions as an isolation layer having a low-impurity density. Although not shown in FIGS. 2A through 2D, a channel doping layer may be formed on the read gate 7 in the vicinity of the substrate surface to adjust a threshold voltage. A gate insulating film 9 made of silicon dioxide or silicon nitride is deposited on the surface of the P well 2 of the silicon substrate, and transfer electrodes 10 and 11 made of polysilicon film are formed thereon. A gate insulating film 12 formed of silicon dioxide is also deposited between the transfer electrodes 10 and 11. A light-shielding film (not shown) made of tungsten or aluminum is overlaid, deposited on an intervening insulating film (not shown) made of silicon dioxide. Furthermore, a cover film (not shown) made of silicon dioxide is deposited thereon.
An explanation will now be given for the reading of electric charges from the photodiodes 101 to the vertical CCD register 102, and the relaying of the received electric charges by the vertical CCD register 102. FIG. 3 is a waveform diagram showing a vertical drive pulse that is commonly employed. In FIG. 3 are shown four drive phases. .phi.V1 through .phi.V4 are applied by regarding, as a period, four readings for transfer electrodes 11, 10, 11 and 10 that are continuous in the vertical direction. Assume that .phi.V2 or .phi.V4 is applied to the transfer electrode 10 and, on the other hand, .phi.V1 or .phi.V3 is applied to the transfer electrode 11 that also serves as a read gate. The reading of electric charges from the photodiode 101 to the vertical CCD register 102 is performed in a vertical blanking period using the high level pulse V.sub.H. The electric charges read for the vertical CCD register are transferred by the vertical CCD register 102 using low and middle level pulses (V.sub.L and V.sub.M). As is shown in FIG. 2D, the transfer electrodes 10 and 11 (more specifically, the coupling lines for connecting, in the direction of columns, the transfer electrodes that correspond to individual pixel strings) overlap, with the insulating film 12 intervening, above the element separation area between the photodiodes 101. Usually, the transfer electrode 10 is located nearer the semiconductor substrate 1 than is the transfer electrode 11. Therefore, for reading, a high-level pulse is not applied to the transfer electrode 10 in the isolation area between the photodiodes 101, and element separation is performed.
The superior feature of this prior art is that the isolation area between the transfer channel (the second N diffusion layer 5) of the vertical CCD register 102 and the photodiode string is uniform.
It is well known that a P diffusion layer, which is an isolation area, is commonly not provided for the read gate 7 (regardless of whether or not there exists a channel doping layer for suppressing a threshold voltage of the read gate). When the width of the transfer channel is 2 .mu.m or smaller and the effects derived from the short channel becomes noticeable, a problem arises in that unwanted barriers and dips are generated, in the transfer direction, in the distribution of the potentials along the transfer channel. Since, in this prior art, the isolation area is uniform along the transfer channel, there is no deterioration of the transfer efficiency.
Currently, in consonance with the increase in the number of pixels and in the density employed for a solid-state image pickup device, the area of the unit pixel 103 has been reduced to 5 .mu.m, square. Accordingly, the width of the isolation area between the pixel strings, or between the first and the second N diffusion layers 3 and 5, has been reduced to approximately 0.5 .mu.m. When the junction depth of the second N diffusion layer 5 is 0.4 to 0.5 .mu.m, and when the junction depth of the first diffusion layer 3 of the photodiode is about 1 .mu.m, in a portion 0.4 to 0.5 .mu.m below the substrate surface, a punch-through to the second N diffusion layer 5 tends to occur.
A problem that arises when a punch-through has occurred will now be explained while referring to FIGS. 4 to 6. FIG. 4 is a graph showing the schematic relationship between substrate voltage V.sub.SUB and output voltage V.sub.OUT. The output voltage is constant when the substrate voltage is V.sub.SUB0 or lower. This area is a voltage area where photodiode blooming can not be controlled by adjusting the substrate voltage, and is not normally used. The phenomenon called photodiode blooming occurs when irradiation with a strong light causes an excessive amount of electrons in the photodiode and to leak to the vertical CCD register via, for example, the read gate area at a time other than during a reading period, and when a false signal shaped like a white, vertical belt is displayed on a pick-up image. As a well known technique for suppression of photodiode blooming, there is a vertical overflow drain (VOD) structure with which the potential of the P well 2, which is formed under the first N diffusion layer 3 in the photodiode, is controlled by adjusting the substrate voltage, so that when an excessive amount of electrons in the photodiode occurs, the electrons will be discharged toward the substrate to avoid their leaking into the vertical CCD register. That is, referring to FIG. 4, a voltage area at V.sub.SUB0 or higher is an area where photodiode blooming can be controlled. The higher the substrate voltage goes, the greater is the number of electric charges that are discharged to the substrate side, and the more the output value is reduced.
FIG. 5 is a schematic graph showing the photodiode blooming suppression characteristic. The horizontal axis represents middle level V.sub.M of the vertical drive pulse, and the vertical axis represents substrate voltage V.sub.SUB. The vertical drive pulse is generally a three-value pulse. When the electric charges are to be read from the photodiode to the vertical CCD register, a pulse of, for example, 15 V (high level: V.sub.H) is applied to the transfer electrode 11, and when the received electric charges are to be transferred in the vertical CCD register, a pulse that is changed, for example, from -7 V (low level: V.sub.L) to 0 V (V.sub.M) is applied to the transfer electrodes 10 and 11 at a predetermined timing. Curve 1 depicts a case where no punch-through has occurred between the photodiode and the vertical CCD register, and curves 2 and 3 depict cases where punch-throughs have occurred. Since along curve 1 the area between the photodiode and the vertical CCD register is cut off, the substrate voltage V.sub.SUB0 is constant in the area at V.sub.M0 or below. Points on the individual curves, from the view point of electric charges that have been generated at the photodiode, correspond to the heights of potential barriers on the substrate side and on the vertical CCD register side, where the read area is present, are equal. In other words, photodiode blooming is inhibited in the area above the curves. With V.sub.M being set to V.sub.M1, the substrate voltage required for inhibiting photodiode blooming is V.sub.SUB1 when no punch-through has occurred between the photodiode and the vertical CCD register, while it is V.sub.SUB2 when a punch-through has occurred. The substrate voltages V.sub.SUB1 and V.sub.SUB2 are 1 V higher than those at the points on the curves 1 and 2 corresponding to V.sub.M1. As is apparent from FIG. 4, a problem has arisen in that when a punch-through has occurred, the output voltage is V.sub.OUT2, which is considerably lower than the output voltage V.sub.OUT1 when no punch-through has occurred. Although like the curve 1, the curve 3 in FIG. 5, which passes through the substrate voltage V.sub.SUB0 at V.sub.M1, can be provided by slightly increasing the density of the element separation layer (the second P diffusion layer 8-2) that has a low impurity density, from this a new problem will arise. A description of this problem follows.
FIG. 6 is a schematic graph showing the characteristic for reading an electric charge from the photodiode to the vertical CCD register. The horizontal axis represents the high level V.sub.H of a vertical drive pulse, the vertical axis represents an output voltage V.sub.OUT, and when curve 4 represents a case where no punch-through has occurred, between the photodiode and the vertical CCD register, curve 5 represents a case where a punch-through has occurred. The knee-points on the curves identify reading completion voltages for the individual cases. As is apparent from FIG. 6, the reading completion voltage V.sub.H2 when a punch-through has occurred is higher than the reading completion voltage V.sub.H1 when no punch-through has occurred. This is because when a punch-through has occurred the reading of electric charges is mainly performed along a channel that is formed in a portion deep inside the substrate, for example, 0.3 to 0.5 .mu.m below the surface, and the reading is less affected by variation in a gate voltage than would be a reading that is performed along a channel at the surface. More specifically, as is shown by the curve in FIG. 5, an increase in the density of the isolation layer (the second P diffusion layer 8-2) that has a low impurity density causes a rise in the reading voltage, and it is difficult, therefore, to avoid a punch-through by controlling the impurity density of only the isolation layer that has a low impurity density. In other words, isolation function between the photodiode and the vertical CCD register in the pixel string is insufficient.